This invention relates to a central processing unit (CPU) for an electronic data processing system and, more particularly to a CPU which permits expansion of the number of processor operations which can be defined by the operation code (op-code) part of an instruction without increasing the op-code field in the instruction.
The op-code of an instruction is a group of binary digits (bits) that define a processor operation such as ADD, SUBTRACT, COMPLEMENT, etc. The set of processor operations formulated for a CPU depends on the processing it is intended to carry out. The total number of distinct operations which can be performed by the CPU determines its set of processor operations.
The number of bits which form the op-code (op-code field) is a function of the number of operations in the set. At least N bits are necessary to define 2.sup.N or less distinct operations. The CPU designer assigns a different bit combination (i.e., op-code) to each operation. The controller section of the CPU detects the bit combination at the proper time in a sequence and produces proper command signals to required destinations in the CPU to execute the specified operation.
In addition to specifying a processor operation, an instruction will normally also carry other information such as the address(es) of memory locations where operand(s) to be used in the processor operations are stored. Ordinarily, the number of bits required for the operand address(es) (address field) occupy most of the bit positions available in the instruction leaving only a limited number of bits to be allocated for the op-code field. When a CPU designer finds the bits allocated to the op-code field insufficient for a given set of processor operations he has, heretofore, had the choice of either accepting a smaller set of processor operations or lengthening the instruction.
Long instructions are disadvantageous in small data processing systems where the memory capacity for storing instructions is limited. In addition, small systems have limited word sizes as well (as small as 4 bits in some systems where the CPU is in the form of a microprocessor), and a long instruction has the added disadvantage of requiring many memory references for retrieval and, thus, of slowing down CPU operation. However, from the standpoint of versatility, programming convenience, and operating efficiency, it is desirable to have a large set of processor operations. Therefore, a problem in designing a CPU for small data processing systems is that of being able to define a large set of processor operations while minimizing instruction length.
Prior art techniques for conserving the lengths of instructions have been directed towards reducing the length of the address field by using some form of abbreviated addressing of memory locations, such as the indirect addressing method or the relative addressing method of extending the address code. A discussion of these techniques can be found in a book entitled Computer Logic Design by M. M. Mano, published by Prentiss-Hall Inc., Englewood Cliffs, N.J., 1972, on pages 343-350, and in U.S. Pat. No. 3,292,151. However, additional reduction of the instruction length can be achieved if an N-bit op-code field in the instruction can be used to define more than 2.sup.N processor operations.